Composite Model Frame(g1)

• Block definition:
  • Name: Frame H
  • Title: {''}

Graphic

Slot Links

• Gov: Gov
• AVR: AVR
• Hydro turbine: Hydro turbine

Parameters

Slot Model: Gov

Slot Model: AVR

Slot Model: Hydro turbine

Block Defintions (Graphical)

Gov

Title

None

Grafic

Subblocks

• +-0.1
• 0[1/s]1
  • States mapping: x2 (x),
• 1
• 1/(1+s2)
• 5
• PI controller
  • States mapping: x1 (x),
• Sigma

Output signals

['z']

Input signals

['xspeed', 'pgt', 'P0']

States

['x', 'x1', 'x2']

Parameters

['Sigma']

Equations

inc(x2)=z

inc(x1)=z

inc(x)=pgt

inc(P0)=(pgt*Sigma-1+xspeed)/Sigma

AVR

Title

None

Grafic

Subblocks

• (1)
• +-C
• -1
• 0[1/s]L2
  • States mapping: x2 (x),
• 10
• G(1+sTa)/(1+sTb)
  • States mapping: x1 (x),
• Pss_act
• ifdlim
• sK/(1+sT)
  • States mapping: x3 (x),
  • Internal variables mapping: dx1 (dx),
• (1+sT1)/(1+sT2)
  • Parameters mapping: T1 (T2),
  • States mapping: x4 (x),
  • Internal variables mapping: dx2 (dx),
• (1+sT1)/(1+sT2)
  • States mapping: x5 (x),
  • Internal variables mapping: dx3 (dx),
• Switch
• [L11/s
• min

Output signals

['ve']

Input signals

['ie', 'V0', 'ut', 'xspeed']

States

['x', 'x1', 'x2', 'x3', 'x4', 'x5']

Parameters

['array_t', 'ifdlim', 'Ta', 'Tb', 'G', 'Kp', 'Tw', 'T1', 'T2', 'PSS_act', 'C']

Upper limitation parameters

['L2']

Lower limitation parameters

['L1']

Equations

inc(x2)=ve

inc(x1)=ve/G

inc(x)=L1!0

inc(x5)=0

inc(x4)=0

inc(x3)=xspeed*Kp

inc0(V0)=ut + ve/G

Hydro turbine

Title

None

Grafic

Subblocks

• (q/z)^2
• 1/Tw
• 1/s
• 1

Output signals

['pt']

Input signals

['z']

States

['x']

Parameters

['Tw']

Equations

inc(x)=pt

inc(z)=pt

Block Definitions (Macros)

(1)

Output signals:

['yo']

Input signals:

['yi']

Parameters:

['array_t']

Equations:

yo=lapprox(yi,array_t)

(1+sT1)/(1+sT2)

Title:

Lead-lag block

Output signals:

['yo']

Input signals:

['yi']

States:

['x']

Parameters:

['T1', 'T2']

Equations:

limits(T2)=(0,)

dx=(yi-x)/T2

x.=dx

yo=x+T1*dx

(q/z)^2

Output signals:

['yo']

Input signals:

['z', 'q']

Equations:

yo=(q/z)*(q/z)

+-0.1

Title:

simmetrical Limiter

Output signals:

['yo']

Input signals:

['yi']

Equations:

yo=lim(yi,-0.1,0.1)

+-C

Title:

simmetrical Limiter

Output signals:

['yo']

Input signals:

['yi']

Parameters:

['C']

Equations:

yo=lim(yi,-C,C)

-1

Output signals:

['yo']

Input signals:

['yi']

Equations:

yo=-1*yi

0[1/s]1

Output signals:

['yo']

Input signals:

['yi']

States:

['x']

Equations:

x.=yi

yo=limstate(x,0,1)

0[1/s]L2

Title:

integrator with anti.windup limits

Output signals:

['yo']

Input signals:

['yi']

States:

['x']

Upper limitation parameters:

['L2']

Equations:

x.=yi

yo=limstate(x,0,L2)

1

Output signals:

['yo']

Equations:

yo=1

1/(1+s2)

Title:

First order delay (PT1)

Output signals:

['yo']

Input signals:

['yi']

States:

['x']

Equations:

x.=(yi-x)/2

yo=x

1/Tw

Output signals:

['yo']

Input signals:

['yi']

Parameters:

['Tw']

Equations:

yo=yi/Tw

1/s

Title:

integrator with anti.windup limits

Output signals:

['yo']

Input signals:

['yi']

States:

['x']

Equations:

x.=yi

yo=x

10

Output signals:

['yo']

Input signals:

['yi']

Equations:

yo=10*yi

5

Output signals:

['yo']

Input signals:

['yi']

Equations:

yo=5*yi

G(1+sTa)/(1+sTb)

Title:

Lead-lag block

Output signals:

['yo']

Input signals:

['yi']

States:

['x']

Parameters:

['Ta', 'Tb', 'G']

Equations:

limits(Tb)=(0,)

dx=(yi-x)/Tb

x.=dx

yo=(x+Tadx)G

L1[1/s

Title:

integrator with anti.windup limits

Output signals:

['yo']

Input signals:

['yi']

States:

['x']

Lower limitation parameters:

['L1']

Equations:

x.=yi

yo=limstate(x,L1,999)

PI controller

Title:

PI controller

Output signals:

['yo']

Input signals:

['yi']

States:

['x']

Equations:

! Proportional Integral controller

x.=0.4*yi

yo=2*yi+x

Pss_act

Output signals:

['yo']

Input signals:

['yi']

Parameters:

['PSS_act']

Equations:

yo=select(PSS_act=0,0,yi)

Sigma

Output signals:

['yo']

Input signals:

['yi']

Parameters:

['Sigma']

Equations:

yo=yi*Sigma

Switch

Output signals:

['yo']

Input signals:

['y1', 'y', 'y2']

Equations:

yo=select(y<0,y2,y1)

ifdlim

Output signals:

['yo']

Parameters:

['ifdlim']

Equations:

yo=ifdlim

min

Output signals:

['yo']

Input signals:

['y1', 'y2']

Equations:

yo=min(y1,y2)

sK/(1+sT)

Title:

First-order lag derivative with gain

Output signals:

['yo']

Input signals:

['yi']

States:

['x']

Parameters:

['Kp', 'Tw']

Equations:

limits(Tw)=(0,)

dx=(Kp*yi-x)/Tw

x.=dx

yo=dx